1. Technical Field
The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor memory apparatus with an enhanced prefetch capability.
2. Related Art
The operational speed of a semiconductor memory apparatus may be enhanced by increasing a data output bandwidth. To this end, the prefetch concept has been introduced. With the prefetch operation, data are simultaneously read from a plurality of memory cells composing a unit cell array, then latched, and sequentially outputted.
As the number of data that are simultaneously read, that is, a prefetch rate increases, the data processing rate may be increased. However, the increase in the prefetch rate accompanies an increase in the number of main amplifiers and global input/output lines, which may ultimately result in sacrifice of a core area.
FIG. 1 is a conceptual diagram of a conventional semiconductor memory apparatus.
FIG. 1 illustrates a semiconductor memory apparatus with an 8-bank structure (B0 to B7). One bank 10 includes an upper bank B0_U and a lower bank B0_L, and each of the upper and lower banks B0_U and B0_L includes eight octets. Furthermore, each octet includes two unit cell arrays and a peripheral circuit.
FIG. 2 is a configuration diagram of a unit octet in the semiconductor memory apparatus shown in FIG. 1.
Each of unit cell arrays 0 and 1 includes a plurality of memory cells coupled between a bit line and a word line (not shown). Furthermore, bit-line sense amplifiers (BLSAs) SA0 to SA3 and SA4 to SA7 are connected to bit line pairs of memory cells which constitute the unit cell array.
During a read operation, the BLSAs SA0 to SA7 primarily amplify data signals from a selected memory cell and provide the amplified data signals to local input/output lines LIO_0 to LIO_7.
The data provided to the local input/output lines LIO_0 to LIO_7 are transferred to main amplifiers MA0 to MA7, which are input/output sense amplifiers, and the transferred data are secondarily amplified by the main amplifiers. When a sensing enable signal is activated, the main amplifiers MA0 to MA7 provide the secondarily amplified data signals to global input/output lines GIO_0 to GIO_7.
The data provided to the global input/output lines GIO_0 to GIO_7 are outputted to output pads according to a designated sequence. For this operation, such components as multiplexers or pipe latches may be required.
In the current 8-bank semiconductor memory apparatus, one octet comprises eight main amplifiers and eight global input/output lines as described above. Therefore, 64 main amplifiers and 64 global input/output lines are required for the upper bank, and equal numbers of main amplifiers and global input/output lines are required for the lower bank.
Therefore, one bank includes 128 main amplifiers and 128 global input/output lines.
Each of the global input/output lines is designed to have a length of several thousand μms, and the main amplifier should be designed to sufficiently drive the corresponding global input/output line. Furthermore, the width of the global input/output lines is preferably increased to achieve low impedance.
As such, the main amplifier and the global input/output line occupy a large area. Therefore, as the prefetch rate increases, the sacrificed area of the core inevitably increases. Furthermore, even when the bandwidth should be increased, the area occupied by the main amplifier and the global input/output line should be considered. Therefore, there is a limit in implementing a high-speed semiconductor memory apparatus.